1. Field of the Invention
This invention relates to integrated circuit testing and repairable memory arrays, and more particularly to built-in self-test (BIST) circuits and methods implemented on integrated circuits for testing embedded memory arrays and the use of BIST data for guiding repair of the embedded memory arrays.
2. Description of the Related Art
Advances in integrated circuit fabrication technology continue to enhance the ability to form increasingly more circuitry upon integrated circuit chips. As the complexity of circuitry formed upon chips increases, the complexity of the testing required to ensure the circuitry functions correctly also increases. However, conventional testing using external test equipment is made extremely difficult as much of the circuitry formed on integrated circuit chips is typically not controllable or observable from input/output (I/O) pads. This is especially true of memory arrays formed along with random logic circuitry upon integrated circuit chips (i.e., embedded memory arrays). A solution to the chip testing problem increasingly being adopted is to incorporate testing circuitry along with the operational circuitry upon the integrated circuit chips themselves. Built-in self-test (BIST) circuitry is one example of such testing circuitry. Array BIST (ABIST) circuitry is commonly used to test proper operation of embedded memory arrays.
Deterministic testing of a memory array allows each and every memory cell of the memory array to be tested in view of one or more fault models. Some known deterministic ABIST circuits embody fixed state machines and store or generate selected test patterns. Such hardwired ABIST circuits must be modified to incorporate additional testing capabilities. For example, logic circuitry used to form the state machine may have to be redesigned to accommodate a new testing algorithm. Circuitry used to generate a test pattern must be modified to generate a different test pattern, and stored patterns must be altered to allow different test patterns to be used during testing. Most importantly, ABIST circuitry typically cannot be modified after chip fabrication, meaning that a given chip can only test an embedded memory array with the testing capabilities embodied within the ABIST circuitry when the chip was fabricated.
Other known types of ABIST circuits allow testing patterns to be serially scanned into an internal register prior to testing. For example, circuitry used to implement Joint Test Action Group (JTAG) boundary scan testing may also be used to serially scan in a testing pattern for ABIST. However, external circuitry must generate and/or provide the testing pattern, adding to the cost and complexity of the ABIST system. In addition, hardwired portions of the ABIST circuitry may still need to be redesigned to accommodate a new testing algorithm.
Memory cells of memory arrays are typically arranged in orthogonal rows and columns. Embedded memory arrays occupying sufficient chip area to impact chip yield are typically fabricated with redundant rows and/or columns. Following chip fabrication, rows and/or columns of the memory array which do not function correctly may be replaced by the redundant rows and/or columns, thus repairing the memory array and improving chip yield. Replacement mechanisms include current-blown fuses and laser-blown fuses. Various built-in self-repair (BISR) techniques use fault location information from BIST circuits to automatically replace rows and/or columns of the memory array which do not function correctly with redundant rows and/or columns, thus performing automatic memory array repair. BISR eliminates the need for external equipment (e.g., a laser) in order to effectuate memory array repair.
It would thus be desirable to have a programmable BIST system for functionally testing embedded memory arrays. Such a programmable BIST system would not require hardware modification to implement additional testing capabilities (e.g., new testing algorithms). The programmable BIST system may provide fault location information in addition to fault detection data, and the fault location information may be used to guide repair of the embedded memory arrays.
An apparatus and method are presented for programmable built-in self-test (BIST) and built-in self-repair (BISR) of an embedded memory (i.e., a memory formed with random logic upon a semiconductor substrate). A semiconductor device including a memory unit may also include a BIST system comprising a BIST logic unit coupled to the memory unit and a master test unit coupled to the BIST logic unit. The master test unit is further coupled to the memory unit. The memory unit receives address signals, data input signals, and control signals. The memory unit stores the data input signals in response to a first set of address and control signals, and provides the stored data input signals as data output signals in response to a second set of address and control signals. The BIST logic unit is configured to store a memory test pattern (e.g., multiple binary digits forming a pattern of 1s and/or 0s). For example, the background pattern described below may be a type of memory test pattern. During BIST, the master test unit provides the memory test pattern to the BIST logic unit and generates the first and second sets of address and control signals. The BIST logic unit produces the data input signals dependent upon the memory test pattern, provides the data input signals to the memory unit, receives the data output signals from the memory unit, and compares the data output signals to the data input signals to form BIST results.
The BIST system may be configured to perform a hardwired BIST routine and/or a programmable BIST routine. The BIST system may perform the hardwired BIST routine when an asserted RESET signal is received by the semiconductor device, and may perform the programmable BIST routine under software control. The master test unit may include a hardwired BIST table for storing unalterable BIST control data and an unalterable memory test pattern. When the RESET signal is asserted, the master test unit may retrieve the unalterable BIST control data and the unalterable memory test pattern from the hardwired BIST table, provide the unalterable memory test pattern to the BIST logic unit, and generate the first and second sets of address and control signals according to the unalterable BIST control data.
The semiconductor device may further include a special register block. The special register block may include one or more addressable registers for storing a programmable memory test pattern, BIST control data, and an access ID code, and the master test unit may be coupled to the special register block. When a predetermined access ID code is stored within the one or more addressable registers, the master test unit may retrieve the programmable memory test pattern and the BIST control data from the one or more addressable registers, provide the programmable memory test pattern to the BIST logic unit, and generate the first and second sets of address and control signals according to the BIST control data.
The memory unit includes multiple memory cells. During the hardwired and/or the programmable BIST routines, the master test unit may generate the first and second sets of address and control signals such that a data input signal is stored within and retrieved from each of the of memory cells of the memory unit at least once. As a result, each and every memory cell of the memory unit is functionally tested.
The memory unit may include multiple copies of a memory structure (e.g., columns, rows, etc.) The BIST logic unit may include one or more redundant memory structures, and the BIST logic unit may be configured to functionally replace a defective memory structure of the memory unit with one of the redundant memory structures dependent upon the BIST results. For example, the BIST logic unit may include one or more redundant rows, and the BIST logic unit may be configured to functionally replace a defective row of the memory unit with one of the redundant rows dependent upon the BIST results.
A microprocessor is described including a CPU core for executing instructions, multiple memory units (e.g., separate instruction and data caches), multiple BIST logic units each coupled to a different one of the memory units, a master test unit coupled to the BIST logic units and to the memory units, and the special register block described above coupled between the CPU core and the master test unit. During instruction execution, the CPU core produces a memory test pattern and stores the memory test pattern within the one or more addressable register of the special register block. The master test unit retrieves the memory test pattern from the special register block, provides the memory test pattern to each of the BIST logic units, and generates the first and second sets of address and control signals. Each BIST logic unit receives the memory test pattern, stores the memory test pattern within a background register, and produces the data input signals dependent upon the memory test pattern. Each BIST logic unit provides the data input signals to the memory unit coupled thereto, receives the data output signals from the memory unit, and compares the data output signals to the data input signals to form BIST results.
The CPU core may produce an access ID code during instruction execution and store the access ID code within the one or more addressable registers of the special register block. When the CPU core stores a predetermined access ID code within the one or more addressable registers, the master test unit may retrieve the memory test pattern from the special register block, provide the memory test pattern to each of the BIST logic units, and generate the first and second sets of address and control signals. The CPU core may also produce BIST control data during instruction execution and store the BIST control data within the one or more addressable registers. The master test unit may retrieve the BIST control data from the one or more addressable registers and generate the first and second sets of address and control signals according to the BIST control data.
Each memory unit of the microprocessor may include multiple copies of a memory structure as described above. Each BIST logic unit may include one or more redundant memory structures, and may be configured to functionally replace a defective memory structure of the memory unit coupled thereto with one of the redundant memory structures dependent upon the BIST results. For example, each memory unit may include multiple row structures. Each BIST logic unit may include one or more redundant row structures, and may be configured to functionally replace a defective row structure of the memory unit coupled thereto with one of the redundant row structures dependent upon the BIST results.
A method for testing a memory unit of a semiconductor device includes storing test data within one or more registers of the semiconductor device, wherein the test data includes a memory test pattern. A predetermined value is then written into a portion of the one or more registers in order to initiate testing of the memory unit. The memory test pattern is retrieved from the one or more registers and used to produce data input signals. The data input signals are provided to the memory unit such that the data input signals are stored within the memory unit. Data output signals are retrieved from the memory unit and compared to the data input signals in order to produce a test result.
A computer system is described including the above microprocessor. The computer system may include a bus coupled to the microprocessor and a peripheral device coupled to the bus. The bus may be a peripheral component interconnect (PCI) bus, and the peripheral device may be, for example, a network interface card, a video accelerator, an audio card, a hard disk drive, or a floppy disk drive. Alternately, the bus may be an extended industry standard architecture (EISA)/industry standard architecture (ISA) bus, and the peripheral device may be, for example, a modem, a sound card, or a data acquisition card.